1. Field of the Invention
The present invention relates to a dropper type regulator, provided with an overload protection function.
Priority is claimed on Japanese Patent Application No. 2006-311469, filed Nov. 17, 2006, the entire contents of which are incorporated herein by reference.
2. Description of the Related Art
A dropper type regulator of the prior art has an overload protection circuit such as that shown for example in FIG. 5.
In FIG. 5, a semiconductor device Q1 and a current detection resistor R5 are connected in series between the positive (+)-side terminal (positive terminal) of a DC power supply 100 and the voltage output terminal Tout, and a smoothing capacitor C2 is connected between the voltage output terminal Tout and the GND (ground) terminal.
The DC power supply 100 has a first voltage (first DC voltage). This first voltage becomes a second voltage (second DC voltage) due to the voltage drop across the semiconductor device Q1, and is output, as a voltage +Vo1, to the voltage output terminal Tout. That is, the dropper type regulator causes a drop in the power supply voltage Ein of the DC power supply 100, and outputs it as the power supply voltage +Vo1.
The semiconductor device Q1 is an N-channel MOS transistor. A bias resistor R1 is connected in parallel between the drain terminal and the gate terminal of the MOS transistor.
A resistor R2 and a shunt regulator Z1 are connected in series between the gate of the semiconductor device Q1 and the ground point GND. The resistor R2 is inserted between the gate of the semiconductor device Q1 and the cathode K of the shunt regulator Z1.
Resistors R3 and R4 are connected in series between the voltage output terminal Tout and the ground point GND. The reference terminal R of the shunt regulator Z1 is connected to the point Q connecting the resistors R3 and R4.
A capacitor C1 is connected between the cathode K of the shunt regulator Z1 and the connection point Q.
The inverting input terminal of a comparator COMP1 is connected to the source terminal of the semiconductor device Q1, and the non-inverting input terminal is connected to the positive electrode of a reference power supply 200 (voltage Vref1). The negative electrode of the reference power supply 200 is connected to the voltage output terminal Tout.
The output terminal of the comparator COMP1 is connected to the input terminal IN of a latch circuit LATCH. The output terminal OUT of the latch circuit LATCH is connected to the gate terminal of the semiconductor device Q1.
Next, referring to FIG. 5, an operation of the overload protection circuit in a conventional dropper type regulator will briefly be explained.
The voltage Ein output by the DC power supply 100 is applied, as a bias voltage, to the gate terminal of the semiconductor device Q1, via the bias resistor R1. By this means, the semiconductor device Q1 turns on state, and current flows in the path through the DC power supply 100, the semiconductor device Q1, the current detection resistor R5, the capacitor C2, and the DC power supply 100, in this order.
Hence, the voltage +Vo1 across the capacitor C2, that is, the output voltage appearing across the voltage output terminal Tout and the GND terminal, reaches a prescribed voltage.
As a result, the voltage across the reference terminal R and the anode A of the shunt regulator Z1 becomes an internal reference voltage (for example, 2.5 V), and the impedance between the cathode K and anode A declines. When the impedance of the shunt regulator Z1 declines, the bias voltage which biases the gate terminal of the semiconductor device Q1 via the resistor R2 declines.
As a result, the impedance of the semiconductor device Q1 rises, and the output voltage +Vo1 declines.
Hence by arbitrarily setting each of the resistors R1, R2, R3 and R4 and the internal reference voltage of the shunt regulator Z1, feedback control can be implemented such that the output voltage is a fixed value. That is, the value of the voltage +Vo1 can be set through the ratio of the resistors R3 and R4. A phase-compensating capacitor C1 is connected between the cathode K and reference terminal R of the shunt regulator Z1, to stabilize the control system.
In the power supply device of the above-described dropper type regulator, the load current flowing to the load from the voltage output terminal Tout is detected by the current detection resistor R5.
Upon detecting that the voltage across the current detection resistor R5 has reached the reference voltage Vref1, the comparator COMP1 outputs L level from the output terminal. This output is input to the input terminal IN of the latch circuit LATCH.
When L level is input, the latch circuit LATCH is set so as to output L level from the output terminal OUT. The latch circuit LATCH may have a delay time, so that there is no operation during rush currents flowing into the capacitor C2 on startup, or during rush currents flowing into capacitors or similar in the load equipment connected between the output terminal Tout and GND terminal.
As explained above, when the load connected to the voltage output terminal Tout increases, the voltage across the current detection resistor R5 rises. When this voltage reaches the reference voltage Vref1, the output of the comparator COMP1 is set to L level, and an overload state is detected. The output terminal OUT of the latch circuit LATCH outputs an L level signal, the voltage applied to the gate terminal of the semiconductor device Q1 is bypassed, and the gate voltage of semiconductor device Q1 is lowered. By this means, when an overcurrent flows in the load, the semiconductor device Q1 is turned off, so that the dropper type regulator provides protection from overloads.
A current-limiting device which controls the IC output current in the dropper type regulator is disclosed in Japanese Unexamined Patent Application, first Publication (JP-A) No. 2005-115601. This current-limiting device has a current-limiting circuit (first current-limiting circuit) which monitors the output current controlled by an output driver transistor external to a voltage regulator IC (constant-voltage source IC) and controls the output current, and a current-limiting circuit (second current-limiting circuit) which monitors the output of an output amplifier within the voltage regulator IC (constant-voltage IC) and performs output current control.
When performing high-precision current limiting, the first current-limiting circuit is selectively operated, and on the other hand when performing low-cost current limiting, the second current-limiting circuit can be selectively operated.
In the conventional current-limiting device, the voltage from the reference voltage circuit is input to an output amplifier and is output to the output terminal via an external output driver transistor. The output at the output terminal is fed back in the output amplifier, compared with the voltage from the reference voltage circuit, and the output driver transistor is controlled to stabilize the output.
The current in an NMOS transistor used in the second current-limiting circuit is controlled based on the output of the output amplifier. The current flowing in the NMOS transistor is detected using a resistor and is limited. The NMOS transistor forms a current mirror together with a transistor which controls the base current of the output driver transistor. Hence a current proportional to the base current of the output driver transistor flows in the NMOS transistor, and so the current of the output driver transistor can be detected. As a result, the output current can be detected without providing an external resistor to detect the current output of the voltage regulator IC.
In recent years, efforts have been made to reduce voltage drops between the input and output in order to suppress to the extent possible losses in dropper circuits. In particular, this has been achieved through the use of MOS-FETs with low on-resistance.
In the example of the conventional art shown in FIG. 5, as already explained, a current detection resistor R5 is inserted for overcurrent protection of the regulator. This current detection resistor R5 must have a resistance sufficient to obtain a certain voltage difference in order to reliably detect the current supplied to the load. That is, in order to perform overload detection, in general the voltage across a current detection resistor R5 is set to approximately 100 mV. Hence, when for example the load current is 10 A, a loss of 1 W occurs in the current detection resistor R5. Hence a resistance sufficiently large to withstand this detected current and voltage must be provided.
As a result, steady-state electrical power losses have been large, and because a resistance having a substantial power rating must be used, costs have been high as well.
Further, when the voltage occurring across the current detection resistor R5 is made low, the comparator employed for load current detection must be more precise. Hence there is the drawback that compared with the cost of the regulator, the overload protection circuit is expensive.
Further, in the device described in JP-A No. 2005-115601, a current mirror circuit which generates a current proportional to the current flowing in the driver transistor must be provided and, moreover, a resistor is necessary to detect the current proportional to the current flowing in the driver transistor, so that there is the disadvantage that the circuit scale is increased.